"We've already seen this happening on the HDL side of things; open-source, research-driven efforts like Clash and Chisel are orders of magnitude better than the crap that industry has been using for years (VHDL and (System) Verilog).
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As someone in the industry, I would have to disagree. I question this every time someone claims it's so awesome. None of those solutions can run simulations on the back annotated netlist . How do you design without a simulation tool that can work at every stage of the design flow?
RTL is a behavioral model. Post synthesis is the physical model. What do you think synthesis engineers do? Just sit around watching the tools run?
Things don't just work automatically. Some idiot can throw a design in that doesn't just synthesize.
After synthesis, your RTL becomes a gate level representation. You then place your logic i.e. Your memory logic near your memories, I/O logic near your pins etc.
You then make clock trees for your various clocks. You don't want related logic clocked by different parts of the clock tree. Once you have stuff physically located, you back annotate and do your static timing analysis.
You generally run simulation on the different stages of synthesis. Someone has to debug all these simulations. They never just pass.
There is a big difference between RTL and gate level simulation. A test passing in RTL is only the 1st stage. RTL doesn't have any wire models so no delays are in there. Gate level sims can run with delays in there.
Synthesis tools can also tell you it doesn't pass timing through static timing analysis but asynchronous parts of the design can't be analyzed. You need simulation there!
Not quite because you have a few more steps in the process after the design phase. For instance, you need to perform testing on the fabricated parts to determine if there are physical defects. That means creating the tests then paying for the testing to be performed at the fabrication place.
Referring to pesticides:
"Organic standards-setting bodies are responsive to new data on toxicity of natural substances and precautionary measured are applied while alternatives are being sought."
"most natural pesticides have a very small persistence in the environment and are, therefore, unlikely to be leave residues in food. Rotenone, for instance, breaks down when exposed to sunlight and has a short lifespan (a week or less) in the environment."
"Research is being undertaken to find alternatives to copper and, meanwhile, organic standards include restrictions on the quantity of copper salt applied to fields."
I studied welding and metal fabrication part time to get my certification. It was a great time. Apart from the physical skills of manipulating metal I really enjoyed the technical drawing aspect. It involved a lot of geometry and visualizing 3D objects.
I think they just broke stuff.
I am talking about harvesting for resources to construct my slum on top of the junkyard of robot parts.
It's not going to cause a problem. The uber robot can auto-claim on its robo-insurance which is less than regular insurance because they don't crash as much. They just have to wait around for their auto tow truck who is having a crazy busy week.
I'm visualizing a future world where a million more homeless people are truck-hopping rather than train-hopping. You summon a delivery robo-truck by stealing all the goods off a shop shelf. It's a bit like calling for a sand worm in Dune.
Can't afford Uber? Just hang onto the roof of one.
That idea came up in conversation among some friends just a couple of days ago! As soon as we have reliable robo-taxis, we're going to have teenagers (and drunk adults) reinventing "train surfing".
However, if I put my business hat on and am preparing to bid on a project, I find myself without a strong argument for favoring RISC-V instead of ARM or MIPS.
I think I agree with you on that. It is still early days for RISC-V and it would be a big risk to use the core in an SoC now. Every time I take a look at it as an SoC engineer I see a lot of work that needs doing to integrate it.
- Basically you would be using a heap of dev tools that you never touched before.
- The bus is something called TileLink which is their own protocol so all your peripherals have to be compatible or wrappers have to be made.
- Verification IP seems minimal and not SystemVerilog so you'd have to write it all yourself.
- Your SW guys would need a good emulator. Don't know if theirs is any good.
Other posts are going on about features but if I think about how much SoC work would be required I question whether it is cheaper than ARM or MIPS.
There are versions based on risc-v (zScale , and something by elkim roa's group) that include APB and AXI bridges . They might be released as open-source.
SystemC tends to be used in prototyping more so than verification for projects I have seen. Can possibly be used to make the system emulator also I think.
My SoC verification projects have been SystemVerilog only so I am not that familiar with SystemC.
Although I believe SystemC can be used for verification, my concern would be how well it performs in simulation together with SystemVerilog components.
Whenever you mix two different languages it usually runs slower. SystemVerilog is already not fast but you are stuck with it since a lot of IP is in SystemVerilog.
Also splitting the verification environment into SystemC and SystemVerilog for different parts would mean the various metrics like coverage from both sides would have to be merged somehow. It would be a challenge to put it lightly I reckon.
Cleaning parks and repairing roads will be done via park cleaning and road repairing robots unfortunately.
The jobs have to be something that can't be automated yet still meaningful. My suggestion is make new jobs in politics. More robots means more political arguments over how to govern them.
They should create extra political positions whenever there is an unemployment problem. It would be just like work but you don't have to produce anything. You just argue amongst yourselves. Make new laws. Repeal old laws. It's very social too.
You don't know what a Bulbasaur is?
Maybe look it up on Wikipedia because as has been mentioned here already there IS an article on Bulbasaur! It is not a stub either.
Yeah it turns out that Bulbasaurus is a very bad example. Sorry. I literally know Pokemon principally as a thing people use to complain about Wikipedia with. I Googled "obscure Pokemon" and will henceforth be using "Kingler" as my example of how unreasonably demanding the Internet is of Wikipedia.
As someone in the industry, I would have to disagree. I question this every time someone claims it's so awesome. None of those solutions can run simulations on the back annotated netlist . How do you design without a simulation tool that can work at every stage of the design flow?
RTL is a behavioral model. Post synthesis is the physical model. What do you think synthesis engineers do? Just sit around watching the tools run?