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On a semi-related note, Google has also been investigating in improving support for SystemVerilog support in open source tooling -> https://opensource.googleblog.com/2021/09/open-source-system...


All these are good points but missed a key thing.

The interchange format includes a computer readable description of the FPGA which tells the tooling what is available inside the FPGA and how they can be connected.


Except that nextpnr is one of the tools supporting the interchange format and you can see the status at https://symbiflow.github.io/fpga-interchange-tests/


Project F (https://projectf.io/posts/fpga-graphics/) has a lot of cool examples with visually interesting output.


If you are motivated by learning rather than practical usage, FPGAs are a great way to learn more about how things like CPUs or peripherals can be designed. It is also a way to understand how to evolve hardware and software at the same time.

Two examples that I have been loosely involved with; * Google's CFU playground which is all about profiling and adding small number of new OpCodes to build an accelerator for a specific ML model (http://cfu-playground.rtfd.io/). * The Fomu workshop (https://workshop.fomu.im) which walks though treating an FPGA like an embedded MCU where you can then modify the MCU!


Google has been working on solutions to make it easier to explore this type of issue (and mitigation techniques), see https://opensource.googleblog.com/2021/11/Open%20source%20DD...


Google is working on platforms to make this easier to explore this problem, see https://opensource.googleblog.com/2021/11/Open%20source%20DD...


Does Speedify have an open source client?

I'd be interested in paying for the service but not willing to run closed source software locally and then send all my traffic to it.


Use Speedify as the underlay network then run a self-hosted VPN on top (configure in the UniFi Dream Machine Pro). :)


That works, and has been done before. It can be confusing to run Speedify and the VPN client on the same box, but if there's a Speedify router box with the internet, and another box with the VPN client, it should just work.


just from reading the article, it sounds like speedify does a lot of packet inspection to prioritize traffic. Wouldn't a VPN negate that?


Not at this point, sorry.


FWIW Google is working on improving the support for SystemVerilog in open source tools.

On the developer tooling side, there is https://github.com/google/verible for linting, code formatting and code indexing.

On the actual compilation side with there are https://github.com/alainmarcel/Surelog and https://github.com/alainmarcel/UHDM which are then being coupled with open source tools like Yosys to allow targeting Xilinx 7 Series and Lattice ECP5 FPGA ICs with fully open source flows using fully open source FPGA tools like symbiflow.github.io


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